ПАРАЛЛЕЛЬНОЕ МОДЕЛИРОВАНИЕ НЕИСПРАВНОСТЕЙ МОП-СТРУКТУР

Abstract

Data structures transformations of the healthy MOS-scheme for simulation of thefaults such as source-drain short-circuiting, gate open-circuiting are consider. The transistors which are added into the healthy device to simulate the different kind faults are described. The simulation of the healthy circuit and the circuits with these types of faults reduces to the simulation of the circuit with the added transistors with nonactive(active) gates of those transistors. The logic many-valued simulation of MOS-schemes is surveyed with the use of parallel iterative method X=M&FQQ, where X is the vector of signals in the circuit nodes, M is the operator lub, and Fsymbolizes the parallel computations associated with Boolean equations.