Optimization of the Addressing Scheme in Compositional Microprogram Control Unit with Code Sharing

Abstract

The article is devoted to development of methods of synthesis and optimization of compositional microprogram control units (CMCU) of FPGA (field-programmable logic arrays). For optimization of resources of a system-on-a-chip used at realization of the compositional microprogram control unit the method of a structural reduction. A method for reducing the hardware amount in the circuit of CMCU with code sharing is proposed oriented on FPGA technology. The method is based on the use of three sources of codes classes of pseudoequivalent OLC and a multiplexer to choose one of these sources. Such an approach would reduce the number of LUT elements in the addressing circuit of CMCU. Application of the specified method to the finite state machine of addressing CMCU, under its implementation with FPGA, leads to reduction of the number of LUT-elements in the circuit of the control unit. Results of research of the developed structures are resulted, allowing defining their efficiency and an area of optimum application. An example of the proposed method application is given.