Уменьшение аппаратурных затрат в схеме МПА Мура при реализации на CPLD

Abstract

Method of Moore’s circuit optimization is proposed. The method is based on use of free outputs EMB blocks for representation the codes of classes of pseudoequivalent states. The proposed approach allows to reduce number of PAL macrocells in Moore FSM without decrease of digital system performance. The carried out researches have shown that the method reduces hardware expenses up to 28%.