Reduction in the number of LUTs in logic circuit of Mealy FSM

Abstract

A method is proposed for reducing the hardware amount in logic circuit of Mealy FSM. The methods targets the technology of FPGA. The method is based on using the model of PR-automaton and implementing the system of microoperations with embedded memory blocks. This approach allows reducing the number of LUTs in the FSM’s circuit. The conditions are shown for using the proposed method.